Nowadays, the vast majority of ICs are realized in complementary metal oxide on silicon (CMOS) technology, because of the high feature density that can be realized in this technology. The reduction in CMOS device feature size has further led to an improvement in the switching speeds of CMOS devices such that it has become feasible, at least in terms of switching speeds, to replace bipolar transistors in high-frequency components of ICs such as radio-frequency (RF) components with CMOS devices. This has the advantage that the number of process steps required for manufacturing the IC can be significantly reduced because it is no longer necessary to have two sets of processing steps for realizing components in different technologies.
However, the speed of the semiconductor device is not the only Figure of Merit (FoM) the designer has to deal with. Other parameters that are at least equally important include cut-off frequency and maximum frequency of oscillation (fT and fMAX), transconductance (gm), output conductance (go), matching, and 1/f noise and NF characteristics.
The required values of these performance parameters are not easily achieved with CMOS devices because the decrease in the feature size of CMOS devices has meant that their supply voltage has also been reduced for reliably operating the device and for reducing the power consumption of the IC. Consequently, the circuit design window has been significantly reduced, which introduces major design problems for e.g. power amplifiers or automotive circuits, for instance because the breakdown voltage of the CMOS devices is insufficient for high-voltage applications.
For analog applications, CMOS devices have been modified in many ways to achieve improved performance. Additional processing steps such as dual oxide technology and drain extensions have been introduced to increase the breakdown voltage of the devices, and additional implants, e.g. halo or pocket implants, have been proposed to counter the short channel effects and to control punch through. Such solutions have the drawback that they need additional process steps and/or additional masks, additional process development and qualification, leading to higher cost of the IC. In fact, in submicron CMOS technologies, cost has become a prohibitive factor in solely designing high-performance circuits in CMOS technology for e.g. radio frequency and analog mixed signal application domains. For this reason, mixed technology processes including both CMOS and bipolar transistors have already been used.
It is well known that vertical bipolar transistors are better suited for e.g. high voltage application domains than CMOS devices by virtue of a superior transconductance. Moreover, in a vertical bipolar transistor as suggested by its name, the main current flows vertically through the bulk as opposed to the lateral current flow through the channels of CMOS devices. This makes bipolar transistors much less sensitive to device degradation and allows for high power densities. Exploiting this vertical dimension can yield high breakdown voltages without requiring much extra silicon area compared to a corresponding CMOS device. In other words, bipolar transistors can be added to a CMOS design without significantly adding to the overall cost of the device to be manufactured.
An example of such a low-complexity HBT is shown in FIG. 1. The substrate 10 comprises an active window 14 separated by shallow trench insulations 12, which are typically formed of a suitable oxide. A collector region (not shown) is typically implanted under the active window 14 and is conductively coupled to the collector contact 26. The vertical heterojunction is defined by a base window 16 comprising an epitaxial base region including a monocrystalline portion 16′ and a polycrystalline portion 16″. The transition between these portions is defined by the grain boundary 17. Extrinsic base contacts for contacting the polycrystalline base material 16″ are formed by polysilicon (poly-Si) regions 18 that are isolated from the substrate 10 by gate dielectric 20. The polysilicon regions 18 and gate dielectric 20 may be formed using a CMOS process steps to form the poly-Si gates of the MOS transistors. A poly-Si emitter 24 is located over the base region and electrically insulated from the extrinsic base region 16″ by spacers 22. The emitter 24 typically has an outdiffusion region extending into the base region, which is formed when developing the emitter implant.
The base window 16 and active window 14 are typically not aligned with each other due to the fact that these windows are defined using different masks. In FIG. 1, the active window 14 is larger than the base window 16. Consequently, the location of the grain boundary 17 is determined by the gate oxide 20, as this is an amorphous material inducing polycrystalline epitaxial growth as opposed to the monocrystalline active substrate material inducing monocrystalline epitaxial growth. A drawback of this arrangement is that the overlap between the base contact and the active region causes a significant increase of the base-collector capacitance as indicated in FIG. 2. This capacitance limits the maximum oscillation frequency fmax of the bipolar transistor, which is an important figure-of-merit for high-performance RF transistors. Hence, this overlap is undesirable.
This overlap can be avoided by choosing the base window 16 to be larger than the active window 14, as shown in FIG. 3. This results in the grain boundary 17 to be located closer to the emitter outdiffusion as its location is determined by the polycrystalline epitaxial growth from the STI region 12 bordering the monocrystalline active window 14. It therefore appears that the base-collector capacitance CCB can be simply reduced by choosing the active window 14 to be smaller than the base window 16. Unfortunately, fmax is inversely proportional to √CCBRB, in which RB is the base resistance. As the base resistance is increased by choosing the base window 16 to be larger than the active window 14, simply extending the base window 16 does not guarantee an improvement in fmax. Moreover, a substantial base resistance increases noise levels of a bipolar transistor, and is therefore also undesirable.
A dominant component to the total base resistance is the link resistance 28, which is located under the emitter-base spacer shown in FIG. 3. A reduction in base resistance may therefore be achieved by reducing the link resistance 28. This may for instance be achieved by reducing the width of the spacers 22. Although this is technologically straightforward, the lower limit of such a width reduction is dictated by the fact that the grain boundary 17 should not be in contact with the emitter outdiffusion 24′ as shown in FIG. 4, as it is well-known that this causes emitter-base junction leakage, which destroys the bipolar transistor. In other words, the width of the spacers 22 is not dictated by technological limits but by the position of the grain boundary 17 instead.